U.S. Pat. No. 4,087,795 relates to an electronic store which is produced according to integrated technology and comprises a plurality of electrically programmable storage FETs. The FETs each possess an insulated, floating storage gate and a controllable control gate. The two gates of each storage FET are capacitively coupled to one another and the two gates act upon the main path of the associated storage FET. The storage cells, which are arranged to form a matrix, each contain only one single FET, namely the storage FET whose control gate is in each case connected to a control line of a first matrix dimension and whose drain terminal is in each case connected to a control line of a further matrix dimension. U.S. Pat. No. 4,087,795 explains that a store of this kind can be designed in such manner that all the source terminals of the storage FETs are connected to a common circuit point, that each storage FET is a n-channel FET and possesses enhancement type properties relative to its controllable control gate in the unprogrammed state. Its storage gate is charged with negative charges during programming by means of channel injection. The storage FETs and the associated control unit are arranged on the same semiconductor carrier.
It is also already known (see German Offenlegungsschrift No. 26 01 622) in an electronic store of this kind to connect the read-out voltage to the control lines of the matrix via decoders which select these control lines on the basis of supplied address words which are decoded and which each consist of a plurality of bits. For programming, a programming voltage is connected, instead of the read-out voltage, via these decoders. Decoders of this kind are constructed with the aid of transistors which each require a plurality of transistors for each control line. Furthermore, additional special voltages are required for the execution of these processes (see FIGS. 4, 5, 6 with voltages V1, V2, V3, common ground 16, storage ground 18 in OS 26 01 622. Here again the storage FETs have a floating storage gate. The store can be erased by being exposed to ultraviolet light.
It is also already known to produce integrated circuits having a plurality of transistors in the so-called V-MOS technique (see IEEE Journal of Solid-State Circuits VOL. SC-9, No. 15, October 1974, pages 239 to 250 and VOL. SC-11, No. 5, October 1976, pages 614 to 621). In this technique the individual n-channel FETs are produced with the aid of pyramid-shaped holes which are etched into the semiconductor carrier. It is also possible to produce a plurality of FETs, lying in the same matrix dimension, with the aid of a common, wedge-shaped, etched recess. In any case, the recess has a V-shaped cross-section. These circuits also include an electronic store (see above-mentioned publication, page 617, FIG. 8) which has V-MOS FETs which are employed as storage cells but which do not possess a floating gate. Therefore this is a store which is not electrically programmable in the manner described in U.S. application Ser. No. 750,860. Here again the read-out voltage is supplied via decoders. Stored words each comprising a plurality of bits are in each case read-out and are interrogated by means of a decoder which is provided for the first matrix dimension and which selects one single control line for the word selection. A decoder is provided for the further matrix dimension and which, for the word selection, simultaneously selects for each bit position one of a plurality of control lines provided for each bit position. The operating voltage is connected to the control lines via series resistors. Here again the decoders are constructed from V-MOS FETs which are connected to the aforementioned control lines. Of these V-MOS FETs, in the case of the control lines of the storage FETs not selected for read-out, with respect to each control line, at least one is rendered conductive, whereas for the aforementioned V-MOS FETs which are connected to control lines of the storage FETs selected for read-out, none are rendered conductive. Here again, the relevant control lines are connected to transistor amplifiers which lead to the output terminals of the store. These transistor amplifiers are constructed from V-MOS FETs and planar enhancement transistors. These transistor amplifiers possess outputs which, during operation, are either blocked in high-ohmic fashion or assume one of two given, comparatively low-ohmic electrical states which belong to binary output signals, so-called tri-state outputs (see e.g. Siemens Mikroprozessoren und Mikrocomputer by Hans-Peter Lohmeyer-Bartenstein, pages 28, 29 and McMOS-Handbook, Motorola Semiconductors, First Edition October 1973, pages 6.20, 6.21, 14.29).
The V-MOS technique for storage FETs as employed in the above described known store does in fact have the advantage that the individual n-channel storage FETs each possess a very short channel. They possess a high operating speed and also have the advantage that they consume only a relatively low operating voltage (see "Electronics", 25th December 1975, pages 50 and 51; 1974 IEEE International Solid-State Circuits Conference, pages 112 and 113). However, they have the disadvantage that they do not possess a floating gate and therefore the store which they form is not electronically programmable. In the meantime, V-MOS FETs have also become known which should be employed as storage FETs and which, in spite of the presence of an additional floating storage gate, have the same above described advantageous properties as the other V-MOS FETs (see Supplement to International Electron Devices Meeting 1976, Washington, D.C., Catalogue No. 76 CH 1151-OED, sponsored by Elektron Devices Society of IEEE). However, it is not known to employ V-MOS FETs of this kind in an electronic store having a plurality of matrix dimensions, although V-MOS FETs without a floating storage gate are known to be suitable for the production of a store having a relatively high storage capacity per surface unit.